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Intel/Busicom Agreement

Agreement between Intel & NCM

The following document is a transcription of the Agreement signed by Dr. Robert Norton Noyce of Intel and Mr. Yoshio Kojima of Nippon Calculating Machine Corporation (NCM) in February of 1970 for the manufacture of a set of chips for NCM's Busicom calculators.

This historical project eventually lead to the development of the Intel 4004 and the invention of the microprocessor.

This transcription has been made with the authorizacion of Mr. Yoshio Kojima, President of Busicom Corporation.

Photos of the original document can be found in the following address:


This Agreement entered into as of February 6, 1970, by and between Intel Corporation, a corporation organized under the laws of the State of California, U.S.A. whose head office is located at 365 Middlefield Road, Mountain View, California, U.S.A. (hereafter referred to as Intel) on one part and Nippon Calculating Machine Sales Corporation whose head office is located at 15-4, Uchikanda 2-chome, Chiyoda-ku, Tokyo, Japan, Nippon Calculating Machine Corporation whose head office is located at 27 komatsubara-cho, Kita-ku, Osaka, Japan and ElectroTechnical Industries Corporation whose head office is located at 7 Kanda-Mitoshiro-cho, Chiyoda-ku, Tokyo, Japan, corporations organized under the laws of Japan (hereafter collectively referred to as NCM) on the other part.


Whereas: NCM is a manufacturer of various units of equipment known as Busicom Desk-Top Electronic Calculators and desirous of developing and manufacturing new type electronic calculators using large scale integrated circuits, and

Whereas: INTEL is engaged in designing electronic devices and desirous of manufacturing large scale integrated circuits for NCM to be used for Desk-Top Electronic Calculators (hereafter to be referred to as Products), and

Whereas: NCM desires to purchase "Products" manufactured by Intel upon terms and conditions hereafter set forth. Now, therefore, in consideration of the mutual convenants and obligations herein contained, it is hereby agreed by and between Intel and NCM as follows.

Article I

Products are defined as integrated circuits for read-only-memory-oriented-systems, jointly designed by Intel and NCM during the course of this agreement, now envisioned to include four circuits namely the NCM-ARU, NCM-ROM, NCM-RAM, and NCM-SHR including NCM variations of bit patterns for the NCM-ROM. The above mentioned NCM-ARU, NCM-ROM, NCM-RAM, NCM-SHR shall be equipped with the following capabilities.

NCM-ARU: The NCM-ARU is a single chip which implements and interprets all microinstructions. The NCM-ARU contains 16 general purpose 4-bit registers, a set of 12 bit registers used as a push-down stack, a 4-bit accumulator with a 1 bit carry/link stage, an operation register and instruction decoder.

The NCM-ARU provides a 4 bit data port for communication with the NCM-ROM and NCM-RAM. The NCM-ARU generates a synchronizing signal which indicates the start of an instruction cycle. The NCM-ARU also generates command signals used to control NCM-RAM and NCM-ROM operations. These signal lines can control up to 4 groups of NCM-ROM's and NCM-RAM's. A group consists of up to 16 NCM-ROM's and 4 NCM-RAM's.

The NCM-ARU implements a decimal adjust accumulator instruction so that decimal arithmetic may be easily realized.

NCM-ROM: The NCM-ROM holds 256 8-bit words of read only memory, and communicates with the NCM-ARU over the 4-bit data path. In addition to the data path, a timing and a command signal are received by the NCM-ROM from the NCM-ARU. During one instruction cycle, the NCM-ROM receives 12 bits of address information from the NCM-ARU via the 4-bit data path, and delivers 8-bits of information to the NCM-ARU over this path.

In addition to the read only storage, a 4 bit register is realized on the NCM-ROM chip. This register is provided with 4 external connections and an external control lead so that it may be used as a general purpose input/output register.

NCW-RAM: The NCM-RAM random-access read-write memory realizes 4 registers, each of which stores up to 20 four-bit characters. Of the 20 characters in each register, 4 are status characters which are directly addressed and 16 are data characters which are addressed indirectly. The NCM-RAM communicates with the NCM-ARU via the same 4-bit data path as does the NCM-ROM, and receives the same command and timing signals as do other NCM-ROM's and NCM-RAM's within the same group.

In addition to the random access memory, a 4-bit output register with 4 external terminals is also realized on the chip.

NCM-SHR: The NCM-SHR is a 10-bit static shift register to be used with NCM-ARU, NCM-ROM, and NCM-RAM as an output device. Inputs include a single data line, a single clock line, and an enable line. Ten data outputs are provided and are present only when enabled. An output which is not controlled by the enable input is provided from the last stage of the shift register so that the shift registers may be cascaded.

Article 2 (Exclusivity)

In the event that Intel sells integrated circuits exclusively designed for desk top calculators (other than standard catalogue items) to other manufacturers within 36 months of the date hereof, Intel will refund to NCM a part of the basic development charge as follows:

From the date of contract

1st month $60,000.00   19th month $30,000.00 
2nd month  58,333.00   20th month  28,333.00 
3rd month  56,667.00   21th month  26,667.00 
4th month  55,000.00   22th month  25,000.00 
5th month  53,333.00   23th month  23,333.00 
6th month  51,667.00   24th month  21,667.00 
7th month  50,000.00   25th month  20,000.00 
8th month  48,333.00   26th month  18,333.00 
9th month  46,667.00   27th month  16,667.00 
10th month 45,000.00   28th month  15,000.00 
11th month 43,333.00   29th month  13,333.00 
12th month 41,667.00   30th month  11,667.00 
13th month 40,000.00   31th month  10,000.00 
14th month 38,333.00   32th month  8,333.00 
15th month 36,667.00   33th month  6,667.00 
16th month 35,000.00   34th month  5,000.00 
17th month 33,333.00   35th month  3,333.00 
18th month 31,667.00   35th month  1,667.00 

Article 4 (Keeping of Secret)

All information supplied by one to the other of the parties hereto shall be treated as confidential and neither party shall knowingly or negligently disclose the same during the effective period of this agreement and one year thereafter to any other person, firm, corporation or association. The Intel's supply of its confidential information to NCM shall not be construed as Intel's authorization to NCM for the use of same for the other purposes than to use the Product.

Article 5 (Desire to Purchase)

NCM shall purchase 60,000 kits of products from Intel during the period of 36 months. Kit shall mean minimum of 8 pcs including NCM-SHR.

Article 6 (Treatment of Patent)

In case any patent problems arise in connection with the purchase and sale of "Products" NCM and Intel will cooperate in defense of patent claims against either party.

Article 7 (Supplying of Technical information)

Intel shall make efforts to supply technical information such as photo-mask design and layout, and computer aided design to NCM as much as possible for mutual benefit and progress during the effective period of the agreement.

In case NCM desires after the termination or during the effective period of this Agreement, to get an exclusive license for manufacture of "Products" in Japan and sale of same in Japan as well as to some overseas countries, Intel shall consider such NCM's desire with as much favor as possible, depending upon Intel's then patent situation or NCM's proposed payment terms, etc.

Article 8 (Development)

Intel shall exercise its reasonable best effort within its capability in developing the four MOS integrated circuits for system use in accordance with the objective specification and supplying them to NCM. NCM shall give all information necessary to Intel's above mentioned development and join in that development, as requested by Intel and within the capability of NCM. Separate arrangements shall be made concerning the actual details of the above mentioned help. These four devices shall be NCM-ARU, NCM-SHR, NCM-ROM, NCM-RAM which are presently in development.

Article 9 (Development Charge)

NCM shall pay to Intel the total of $60,000 as the development charge for four devices of NCM-ARU, NCM-SHR, NCM-ROM, NCM-RAM. NCM shall also pay to Intel $2,000 as the tooling charge for each NCM-ROM separately. The time of payment of these charges shall be subject to Article 10.

Article 10 (Incoming Tests of Production Sample)

Intel shall supply to NCM 30 kits of production samples and NCM shall attempt to perform and complete testing of these samples within 30 days, but in no event longer than 60 days, after NCM's receipt of the samples, according to the evaluation test technique approved by Intel. The above mentioned evaluation test technique shall be decided 1 month before the delivery of production samples. If the test result is satisfactory NCM shall place a follow-on order for 3 months out of the delivery schedule decided separately. NCM's obligation to pay the development charge shall start on satisfactory completion of the test of the production samples. NCM shall submit the evaluation test report to Intel. If the result of the evaluation test is unsatisfactory, Intel and NCM shall make an effort to find the cause within 30 days based on the test report.

If the cause can not be fixed, Intel and NCM shall consult for one month in order to find the solution method with a view to smoothly starting NCM's production according to the separate arrangement provided in Article 8. If a satisfactory conclusion can not be found, the parties will go to arbitration as provided in Article 22 for solution.

Article 11 (Incoming Test of Product)

  1. Intel shall supply to NCM Product in full compliance with the acceptance test specifications decided after consultation by the two parties.
  2. The acceptance test of Product shall be applied to the entire delivery and shall be performed within 30 days after NCM'S receipt thereof.
  3. The acceptance test specifications shall be decided 3 months before the delivery of the first production quantity upon separate consultation per Product.
  4. The Intel's sales and delivery of Product to NCM shall be conducted under and governed by the terms and conditions as shown in the Intel's regular invoice form attached hereto as a part of this Agreement, unless contrary to this Agreement.
  5. Intel shall give warranty that Product delivered hereunder shall be free from defects in materials or workmanship according to the specifications for a period of one year from the date of delivery to NCM. Intel's obligation under the warranty is limited to replacement at Intel's plant without charge, of such Product and/or parts thereof which shall be returned freight collect to Intel within the warranty period and as shall be acknowledged by

Article 12

Intel agrees to maintain capability to manufacture Products and to make the Products available for purchase by NCM for a period of not less than 10 years after the date of delivery of the last lot of Products delivered to NCM and such products shall be sufficient that they can be used as replacement for the original products.

Article 13 (Price and Delivery Schedule for Production Quantities of MOS Integrated Circuits)

NCM's delivery requirement shall be as follows:

1st 3 months 1K        7th 3 months 6.5K 
2nd 3 months 6K        8th 3 months 6.5K 
3rd 3 months 6K        9th 3 months 6.5K 
4th 3 months 6.5K     10th 3 months 6.5K 
5th 3 months 6.5K     11th 3 months 5.0K 
6th 3 months 6.5K

Total Kits: 60K Kits

Price/part (device) for the above delivery shall be as follows:

                     NCM-ROM   NCM-ARU 
First     50K    @    $13.00    $19.50 
Second   100K    @     12.00     18.00 
Third    200K    @       
Fourth   400K    @       
Concerning the above table of price/part

  1. The whole price of third delivery parts of 200K shall be renegotiated while NCM still keeps some stock for second delivery parts of 100K.
  2. The whole price of fourth delivery parts of 400K shall be renegotiated while NCM still keeps some stock of third delivery parts of 200K.
  3. Price for NCM-SHR shall be $2.15

Article 14 (Reliability)

It is anticipated that a reliability of 0.01 percent failures per 1,000 hours is a reasonable reliability goal. Intel shall place a sample number of devices on operating life test for a minimum of 1,000 hours. The data obtained from these tests shall be made available to NCM at no charge, and any failures shall be analyzed to determine cause. All shipped circuits shall be processed through Intel standard reliability screening procedures.

Article 15 (Payment)

The method of payment for Products purchased by NCM from Intel shall be documents against acceptance within 120 days after sight. However, after 60 days NCM shall pay interest at U.S. prime rate.

Article 16 (Integration of Agreements)

It shall be agreed that this instrument contains the entire and only agreement between the parties hereto and representations, promises or conditions not specifically set forth or incorporated herein shall not be binding on any party.

Article 17 (Force Majeure)

Neither party shall be responsible for a failure or delay in performance of any of its obligations hereunder due to force majeure such as war, insurrection, strikes, act of God, governmental action or any other contingency beyond its control.

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